Charge stored directly above the channel areas of insulated gate field effect transistors (IGFETs) are known to result in modulation of the IGFET's conductance. This phenomenon is successfully utilized in the manufacturing of EEPROM devices. An EEPROM device comprises a means of charge storage and a means of generating and transporting charge to the charge storage site. The stored charge modulates the channel conductance of the IGFET in such a manner as to achieve a programmed or an erased state of the device.
While an IGFET based memory device can be programmed and erased in a variety of ways, only two basic types of charge storage media can be identified. The charge (information) can be stored on a floating (isolated) gate or in traps purposely introduced in the gate dielectric. Examples of floating gate memory devices are described in U.S. Pat. No. 4,471,471 by Donelli J. DiMaria, issued Sept. 11, 1984; and U.S. Pat. No. 4,432,072 by Hu H. Chao et al, issued Feb. 14, 1984.
The subject of the present invention is a "floating trap" type charge storage media and a memory device utilizing this charge storage media. Introduction of deep traps in a dielectric is commonly achieved by creating a hetero-dielectric structure such as described in U.S. Pat. No. 4,344,222 by David L. Bergeron, issued Aug. 17, 1982. It is also possible, however, to create deep traps by ion implantation of an impurity such as arsenic (As) into the dielectric. Silicon devices (Si) made using such a process are described in U.S. Pat. No. Re. 31,083 by Roger F. DeKeersmaecker et al, issued Nov. 16, 1982.
It has been found that the manufacture of such devices requires high doses of implanted species so that a sufficient number of traps remain after a high temperature annealing process which is required during IGFET fabrication. High doses of implanted arsenic (or other material such as P, Al, W) cannot be adequately confined to a thin dielectric layer due to range straggle and other artifacts of the implantation and subsequent anneal processes. Consequently, some of the species being implanted penetrate the underlying semiconductor substrate resulting in undesirable counter-doping effects. These considerations limited the useful range of dielectric thicknesses to a minimum of approximately 500 Angstroms in prior art devices such as described in U.S. Pat. No. Re 31,083. Furthermore in order to reduce the operating voltages required to transport charge to and from implant induced traps in the devices shown in this patent, additional layers had to be introduced in the gate dielectric to improve charge injection efficiency. The additional layers described in U.S. Pat. No. Re 31,083 are referred to as graded band gap (or stepped band gap) injectors.